A Serializer and Deserializer (SerDes) device is an important building block in high speed computer networks and data communications systems. In applications that use a SerDes device, a clock signal is typically not transmitted with the data signal. Rather, a Clock and Data Recovery (CDR) system in a receiver portion of the SerDes device typically extracts timing information from a received signal and establishes a recovered clock signal. The recovered clock signal is then used to sample the received signal and to detect the transmitted data. The recovered clock signal typically has substantially the same frequency and phase as the received signal.
It is often desired to configure a SerDes device in a host-lock mode, where the transmitter portion of the SerDes device is synchronized to the recovered clock signal generated by the receiver portion of the SerDes device. When the transmitter is synchronized to the recovered clock signal, however, any distortions in the recovered clock signal will impair the transmitted data signal. For example, jitter is an unwanted variation of one or more signal characteristics, such as an interval between successive pulses. Jitter results in the receiver CDR system failing to accurately reproduce the timing information in the recovered clock signal.
In the host-lock mode, any distortion in the recovered clock signal directly and negatively influences the performance of the transmitter. A need therefore exists for improved techniques for synchronizing the transmitter in a SerDes device to the recovered clock signal generated by the local receiver. A further need exists for improved techniques for implementing a host-lock mode that digitally remove the CDR-induced jitter that is inherent in the received signal.